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Официальный интернет-портал Президента Республики Беларусь

Национальная академия наук Беларуси


Грид-сеть высокопроизводительных вычислительных ресурсов Национальной академии наук Беларуси   

Портал рейтинговой оценки качества оказания услуг организациями Республики Беларусь   

БИСРС (Белорусская интегрированная сервисно-расчетная система и биометрические документы)   

CLTT system of throughout design of functional units of super great integrated scheme (VLSI) on the basis of programmed macroelements

CLTT system of throughout design of functional units of super great integrated scheme (VLSI) on the basis of programmed macroelements

Developer company: The United Institute for Informatics Problems of the National Academy of Sciences of Belarus

Contact persons: P.N. Bobilo, tel. 284-20-84,;
V.I. Romanov, 284-20-76,

Product brief description:
CLTT system provides throughout design of functional blocks of custom digital CMOS VLSI from combination microelements with use of initial description of projects in VHDL high-level language. The macroelements of three types can be used as parameterized ones: programmed logical matrixes (PLM), the macroelements with successive regular connections of transistors and ROMs. The system provides a layered topology of macroelements and places them compactly on VLSI crystal field taking into account the technological limitations. The location problems are being solved in specially designed EdTop topological editor. Automatic compilation of macroelements layered topology is being performed under functional descriptions of the parameterized topology fragments. The creation of the sub-schemes SPICE-models, that are realized in the form of macro-PLAs and PMOS-circuits is being held, as well as the converting of layered topology descriptions of sou-format (format of domestic producers topology) into gds format (topology format of Mentor Graphics company).

CLTT system algorithmic and software tools allow to:

  • simplify the information links between designed systems;
  • improve design quality (reduce area and increase the reliability of VLSI);
  • verify the logical phase of macroelements projection;
  • reduce the projection time by automatic generation of macroelements layered topology and by choosing places for macroelements.

The basic version of the system includes four subsystems managed by unified software, and includes the tools for designing process easy management:

  • "Project Forming" subsystem allows to get information of the project as hierarchically organized project in the internal form;
  • "Project Optimization" subsystem is designed to solve problems of logic projecting and optimizes the view of combination part of the project with various limitations and optimization criteria taken into account;
  • "Project Verification" subsystem solves the problem of determining the functional equivalence of different states of the project;
  • "Project Compiling" subsystem is intended to form the layered topological descriptions of macroelements. As a result we get bus networks with the optimization of the number of bus ports.
  • "Project Compiling" subsystem also generates information for organizing macroelements placement on the VLSI crystal field, which is carried out by using «EdTop»integrated topological editor.

The effective algorithms for solving resource-demanding optimization combinative tasks of labor-intensive tasks make the basis of the projecting of logic synthesis and verification, which helps to reduce projection time. Managing the solving of an initial problem is controlled by a user in dialog mode with the help of a system of nested menus and icons. A user can interrupt the process of problem solving and restart it during the next session.

Main advantages:
The significance of the project is the ability to provide secure throughout designing  of the networks of different macronutrients. The system is designed to run on PC and has a user-friendly interface that focuses on skilled VLSI designer, who can take an active part in all stages of decision-making and decision evaluation. The system can be used in the creation of integrated systems of VLSI automated  projecting, manufactured in CMOS technology.

Field of application:
The system can be used at the microelectronics industry enterprises involved in the development of custom VLSI CMOS produced at rates of 0,5-08 mm. The system can also be used at universities for training for "Microelectronics" and "Mathematical electronics" specialties.

Stages of development:
The actual versions of the system have been tested on real design problems of branch of STC "Belmikrosistemy"— JSC "INTEGRAL", where the experts have participated in its development.

Forms of cooperation:
System developers can provide its installation and adaptation to the customer’s needs, specialists training, methodical and software support, participation in the further development.

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